A CMOS integrated circuit consists of an n-channel MOS transistor and a p-channel MOS transistor formed in and on the surface regions of a semiconductor substrate. The two transistors are typically isolated from each other by an insulating material, such as silicon dioxide. When the insulating material is present only on the surface of the substrate, a local oxidation of silicon (LOCOS) process is utilized to form the silicon dioxide layer. The active areas of the substrate containing the n-channel and p-channel transistors are masked with a layer of silicon nitride. The unmasked region of the substrate, between the active areas, is then oxidized to form the isolation region. However, during this oxidation process, the silicon dioxide propagates under the silicon nitride masking layer into the active area regions. This oxide propagation or "bird's beak" reduces the length of the active area region and increases the minimum distance between the p-channel and n-channel transistors. The LOCOS isolation process is not suitable for VLSI circuits because very high circuit densities cannot be achieved.
Trench isolation techniques can also be used to isolate the p-channel and n-channel transistors. In a typical trench isolation process, a trench is etched into the substrate between the two transistors. Then, the side walls of the trench are oxidized before the remainder of the trench is filled with a dielectric material, such as chemically vapor deposited silicon dioxide. The trench isolation process is more suitable for VLSI circuits because it reduces the minimum distance between the n-channel and p-channel transistors.
Isolation regions can also be formed in the field areas of the device using a buried oxide (BOX) process. A trench is first formed in the field areas of the substrate. Then, the walls of the trench are thermally oxidized before an insulating material is used to fill the trench. As in the trench isolation process, the insulating material may be chemically vapor deposited silicon dioxide. In the BOX process, the trenches are generally not as deep as the trenches utilized in a CMOS device to isolate the p-channel and n-channel transistors.
In both the trench isolation technique and the BOX process, there is a problem of positive charges forming on the walls of the trench at the interface with the silicon dioxide layer. The doping concentration at the vertical side wall is dependent on the doping concentration of the adjacent n- or p- silicon substrate or well. If the side wall is lightly doped p-type silicon, the interface positive charge could be sufficient to cause inversion along the wall of the trench. In order to overcome this problem, it has been proposed to increase the doping concentration at the side wall so as to increase the side wall threshold voltage. One such technique has been proposed by G. Fuse et al. in the article entitled "Trench Isolation With Boron Implanted Side-Walls for Contolling Narrow-Width Effect of n-Mos Threshold Voltages," 1985 Symposium on VLSI Technology, Digest of Technical Papers Japan Society of Applied Physics, May 14-16, 1985, pp. 58-9. The trenches are first etched into the silicon substrate using a reactive ion etching technique. Then, the silicon substrate is rotated while boron atoms are implanted into each side wall using an implantation angle of 0.degree. and 8.degree. . This technique is not suitable for CMOS devices because the implantation process is not selective. The side wall adjacent the n-well or n-substrate in the CMOS device would be implanted with the boron atoms.